Equipment overlay tool

Flicker Noise Noise related to resistance fluctuation. Flip-Chip A type of interconnect using solder balls or microbumps. Formal Verification Formal verification involves a mathematical proof to show that a design adheres to a property.

Functional Coverage Coverage metric used to indicate progress in verifying functionality. Functional Design and Verification Functional Design and Verification is currently associated with all design and verification functions performed before RTL synthesis.

Functional Verification Functional verification is used to determine if a design, or unit of a design, conforms to its specification. Gate-Level Power Optimizations Power reduction techniques available at the gate level. Generation-Recombination Noise noise related to generation-recombination. Germany Germany is known for its automotive industry and industrial machinery. Graphene 2D form of carbon in a hexagonal lattice. Guard Banding Adding extra circuits or software into a design to ensure that if one part doesn't work the entire system doesn't fail.

Hardware Assisted Verification Use of special purpose hardware to accelerate verification. Hardware Modeler Historical solution that used real chips in the simulation process. Heat Dissipation Power creates heat and heat affects power. High-Bandwidth Memory HBM A dense, stacked version of memory with high-speed interfaces that can be used in advanced packaging. Hybrid Cloud Combines use of a public cloud service with a private cloud, such as a company's internal enterprise servers or data centers.

Hyperscale Data Centers A data center facility owned by the company that offers cloud services through that data center. IC Types What are the types of integrated circuits? Impact of lithography on wafer costs Wafer costs across nodes. Implementation Power Optimizations Power optimization techniques for physical implementation. In-Memory Computing Performing functions directly in the fabric of memory.

Induced Gate Noise Thermal noise within a channel. Integrated Circuits ICs Integration of multiple devices onto a single piece of semiconductor. Intellectual Property IP A design or verification unit that is pre-packed and available for licensing. Intelligent Self-Organizing Networks Networks that can analyze operating conditions and reconfigure in real time. Inter Partes Review Method to ascertain the validity of one or more claims of a patent. Internet of Things IoT Also known as the Internet of Everything, or IoE, the Internet of Things is a global application where devices can connect to a host of other devices, each either providing data from sensors, or containing actuators that can control some function.

Interposers Fast, low-power inter-die conduits for 2. Ion Implants Injection of critical dopants during the semiconductor manufacturing process. IR Drop The voltage drop when current flows through a resistor. ISO — Functional safety Standard related to the safety of electrical and electronic systems within a car.

Languages Languages are used to create models. Level Shifters Cells used to match voltages across voltage islands. LIN bus Low cost automotive bus. Lint Removal of non-portable or suspicious code. Litho Freeze Litho Etch A type of double patterning. Lithography Light used to transfer a pattern from a photomask onto a substrate. Lithography k1 coefficient Coefficient related to the difficulty of the lithography process.

Logic Resizing Correctly sizing logic elements. Logic Restructuring Restructuring of logic for power reduction. Logic Simulation A simulator is a software process used to execute a model of hardware. Low Power. Low Power Methodologies Methodologies used to reduce power consumption.

Low Power Verification Verification of power circuitry. Low-Power Design. LVDS low-voltage differential signaling A technical standard for electrical characteristics of a low-power differential, serial communication protocol.

Machine Learning ML An approach in which machines are trained to favor basic behaviors and outcomes rather than explicitly programmed to do certain tasks. Manufacturing Noise Noise sources in manufacturing. Materials Semiconductor materials enable electronic circuits to be constructed.

Memory A semiconductor device capable of retaining state information for a defined period of time. Memory Banking Use of multiple memory banks for power reduction.

MEMS Microelectromechanical Systems are a fusion of electrical and mechanical engineering and are typically used for sensors and for advanced microphones and even speakers. Metamaterials Artificial materials containing arrays of metal nanostructures or mega-atoms. Metastability Unstable state within a latch. Methodologies and Flows Describes the process to create a product. Metrology Metrology is the science of measuring and characterizing tiny structures and materials.

Microcontroller MCU. Microprocessor, Microprocessor Unit MPU The integrated circuit that first put a central processing unit on one chip of silicon. Mixed-Signal The integration of analog and digital. Models and Abstractions Models are abstractions of devices. Monolithic 3D Chips A way of stacking transistors inside a single chip instead of a package. Mote A mote is a micro-sensor. Multi-Beam e-Beam Lithography An advanced form of e-beam lithography. Multi-site testing Using a tester to test multiple dies at the same time.

Multi-Vt Use of multi-threshold voltage devices. Multiple Patterning A way to image IC designs at 20nm and below. MXenes A durable and conductive material of two-dimensional inorganic compounds in thin atomic layers. Nanoimprint Lithography A hot embossing process type of lithography. Nanosheet FET A type of field-effect transistor that uses wider and thicker wires than a lateral nanowire.

Near Threshold Computing Optimizing power by computing below the minimum operating voltage. Near-Memory Computing Moving compute closer to memory to reduce access costs. Neural Networks A method of collecting data from the physical world that mimics the human brain. Neuromorphic Computing A compute architecture modeled on the human brain. Noise Random fluctuations in voltage or current on a signal.

Off-chip communications. On-chip communications. Operand Isolation Disabling datapath computation when not enabled. Optical Inspection Method used to find defects on a wafer. Optical Lithography. Overlay where you are The ability of a lithography scanner to align and print various layers accurately on top of each other. Packaging How semiconductors get assembled and packaged. Patents A patent is an intellectual property right granted to an inventor. Pellicle A thin membrane that prevents a photomask from being contaminated.

Phase-Change Memory Memory that stores information in the amorphous and crystalline phases. Photomask A template of what will be printed on a wafer. Photoresist Light-sensitive material used to form a pattern on the substrate. Physical Design Design and implementation of a chip that takes physical placement, routing and artifacts of those into consideration.

Physical Verification Making sure a design layout works as intended. Picocells A small cell that is slightly higher in power than a femtocell. Pin Swapping Lowering capacitive loads on logic. Power Consumption Components of power consumption. Power Cycle Sequencing Power domain shutdown and startup.

Power Definitions Definitions of terms related to power. Power Estimation How is power consumption estimated. Power Gating Reducing power by turning off parts of a design. Power Gating Retention Special flop or latch used to retain the state of the cell when its main power supply is shut off. Power Isolation Addition of isolation cells around power islands. Power Issues Power reduction at the architectural level.

Power Management Coverage Ensuring power control circuitry is fully verified. Power Management IC PMIC An integrated circuit that manages the power in an electronic device or module, including any device that has a battery that gets recharged. Power Supply Noise Noise transmitted through the power delivery network. Power Switching Controlling power for power shutoff. Power Techniques. Power-Aware Design Techniques that analyze and optimize power in a design.

Power-Aware Test Test considerations for low-power circuitry. Private Cloud Data centers and IT infrastructure for data storage and computing that a company owns or subscribes to for use only by that company. Process Power Optimizations power optimization techniques at the process level. Process Variation Variability in the semiconductor manufacturing process. Processor Utilization A measurement of the amount of time processor core s are actively in use.

Processors An integrated circuit or part of an IC that does logic and math processing. Property Specification Language Verification language based on formal specification of behavior.

Public Cloud Data storage and computing done in a data center, through a service offered by a cloud service provider, and accessed on the public Internet. Quantum Computing A different way of processing data using qubits.

Random Telegraph Noise Random trapping of charge carriers. Rare Earth Elements Critical metals used in electronics. Recurrent Neural Network RNN An artificial neural network that finds patterns in data using other data stored in memory. Redistribution Layers RDLs Copper metal interconnects that electrically connect one part of a package to another.

Reliability Verification Design verification that helps ensure the robustness of a design and reduce susceptibility to premature or catastrophic electrical failures.

Reticle Synonymous with photomask. Rich Interactive Test Database RITdb A proposed test data standard aimed at reducing the burden for test engineers and test operations. Root of Trust Trusted environment for secure functions. RVM Verification methodology based on Vera. SAT Solver Algorithm used to solve problems. Scan Test Additional logic that connects registers into a shift register or scan chain for increased test efficiency.

Scoreboard Mechanism for storing stimulus in testbench. Semiconductor Manufacturing Subjects related to the manufacture of semiconductors. Semiconductor Security Methods and technologies for keeping data safe. Sensor Fusion Combining input from multiple sensor types.

Sensors Sensors are a bridge between the analog world we live in and the underlying communications infrastructure. Shift Left In semiconductor development flow, tasks once performed sequentially must now be done concurrently. Short Channel Effects When channel lengths are the same order of magnitude as depletion-layer widths of the source and drain, they cause a number of issues that affect design.

Shot Noise Quantization noise. Side Channel Attacks A class of attacks on a device and its contents by analyzing information using different access methods.

Silicon Photonics The integration of photonic devices into silicon. Simulation A simulator exercises of model of hardware. Simulation Acceleration Special purpose hardware used to accelerate the simulation process. Simultaneous Switching Noise Disturbance in ground voltage. Small Cells Wireless cells that fill in the voids in wireless infrastructure. Software-Driven Verification Verification methodology utilizing embedded processors. Spread Spectrum A secure method of transmitting data wirelessly.

Standard Essential Patent A patent that has been deemed necessary to implement a standard. Standards Standards are important in any industry. Stimulus Constraints Constraints on the input to guide random generation process. Substrate Biasing Use of Substrate Biasing. Substrate Noise Coupling through the substrate.

Switches Network switches route data packet traffic inside the network. System on Chip SoC A system on chip SoC is the integration of functions necessary to implement an electronic system onto a single substrate and contains at least one processor. SystemVerilog Industry standard design and verification language. Testbench Software used to functionally verify a design. Thermal Noise Noise related to heat. Transistors Basic building block for both analog and digital circuits. Transition Rate Buffering Minimizing switching times.

Triple Patterning A multi-patterning technique that will be required at 10nm and below. UL — Standard for Safety for the Evaluation of Autonomous Products Standard for safety analysis and evaluation of autonomous vehicles.

Unified Coverage Interoperability Standard Verification The Unified Coverage Interoperability Standard UCIS provides an application programming interface API that enables the sharing of coverage data across software simulators, hardware accelerators, symbolic simulations, formal tools or custom verification tools. User Interfaces User interfaces is the conduit a human uses to communicate with an electronics device.

Utility Patent Patent to protect an invention. Vera Hardware Verification Language. Verification Methodologies A standardized way to verify integrated circuit designs. Verification Plan A document that defines what functional verification is going to be performed. Verilog Hardware Description Language in use since Verilog Procedural Interface Procedural access to Verilog objects.

Virtual Prototype An abstract model of a hardware system enabling early software execution. VMM Verification methodology built by Synopsys. Volatile Memory Memory that loses storage abilities when power is removed.

Voltage Islands Use of multiple voltages for power reduction. Von Neumann Architecture The basic architecture for most computing today, based on the principle that data needs to move back and forth between a processor and memory.

Wafer Fab Testing Verifying and testing the dies on the wafer after the manufacturing. Wafer Inspection The science of finding defects on a silicon wafer. Wired communications Wired communication, which passes data through wires between devices, is still considered the most stable form of communication. Wireless A way of moving data without wires. X Architecture IC interconnect architecture. X Verification X Propagation causes problems.

Aart de Geus. Adam Kablanian. Aditya Mittal. Adnan Hamid. Adrian Simionescu. Ahmed Hemani. Ajay Daga. Ajoy K. Akash Deshpande. Aki Fujimura. Al Akermann. Alain Fanet. Alain J. Alakesh Chetia. Alan Scott. Alberto Sangiovanni-Vincentelli. Alex Alexanian. Alexander Samoylov. Alisa Yaffa. Allan Douglas. Amir Zarkesh. Amit Gupta. Amit Mehrotra. Amit Narayan. Amit Saxena. Amr Mohsen. An-Chang Deng. An-Yu Kuo. Anant Agarwal. Andrea Casotto.

Andreas Ripp. Andreas Veneris. Andrei Tcherniaev. Andrew Hughes. Andrew T. Andrzej Strojwas. Andy Chou. Andy Goodrich. Andy Huang. Andy Ladd. Andy Lin. Ange Aznar. Anmol Mathur. Anupam Bakshi. Apo Sezginer. Apostolos Liapist.

Aram Mirkazemi. Ari Takanen. Armin Biere. Arnaud Schleich. Arul Sharan. Arvind Mithal. Aryeh Finegold. Asen Asenov. Ashawna Hailey. Ashraf Takla. Asoke K. Atsushi Kasuya. Atul Bhagat.

Atul Bhatia. Aurangzeb Khan. Avideh Zakhor. Avishai Silvershatz. Axel Jantsch. Babu Chilukuri. Badru Agarwala. Barry Katz. Barry Rosales. Bart De Smedt. Becky Cavanaugh. Ben Chelf. Ben Levine. Bendt Sorensen. Bernard Vonderschmitt. Bernie Rosenthal. Bill Berg. Bill Buckie. Bill Childs. Bill Hoover. Bill Krieger. Bill Neifert. Bill Robertson. Bill Sommer. Biman Chattopadhyay.

Bing Yeh. Bob Flatt. Bob Hunter. Bob Quinn. Borgar Ljosland. Boris Gruzman. Brad Quinton. Brian Davenpoort. Bruce M. Bryan Hoyer. Carson Bradbury. Carver Mead. Char Devich. Charles Edelstenne. Charles Evans. Charles J. Chuck Abronson. Charlie Cheng. Charlie Huang. Cheng Wang. Chenming Hu. Chi-Lai Huang. Ching-Chao Huang. Chioumin Michael Chang. Chong Ming Frank Lin. Chouki Aktouf. Chris Schalick. Chris Wilson. Chris Curry. Chris Rosebrugh. Chris Rowen. Christian Masson.

Christophe Alexandre. Chung-Kuan Cheng. Claudio Basile. Cleve Moler. Clifton Cliff Lyons. Clinton W. Coby Zelnik. Colin Hunter. Craig Harris. Craig Honegger. Craig Gleason. Craig Stoops. Cristian Amitroaie. Cyril Spasevski. Cyrus Afghahi. Da Chuang. Damian Smith. Dan Abrams.

Dan Chapiro. Dan Jaskolski. Dan Malek. Danesh Tavana. Daniel Hansson. Dave Gregory. Dave Millman. Dave Moffenbeier. David Marple. David Botting. David Chyan. David Coelho. David E. David Galloway. David Greaves. David Hamilton. David Henke. David Johannsen. David Novosel.

David Overhauser. David Park. David Pellerin. David R. David Stamm. David Stewart. David Yao. Creates a feature class by overlaying the input features with the erase features. Only those portions of the input features falling outside the erase features are copied to the output feature class. Computes a geometric intersection of the input features and identity features. The input features or portions thereof that overlap identity features will get the attributes of those identity features.

Computes a geometric intersection of the input features. Features or portions of features that overlap in all layers or feature classes will be written to the output feature class. Remove Overlap multiple. Removes overlap between polygons contained in multiple input layers.

Spatial Join. Joins attributes from one feature to another based on the spatial relationship. The target features and the joined attributes from the join features are written to the output feature class. Symmetrical Difference.

Computes a geometric intersection of the input and update features, returning the input features and update features that do not overlap. Features or portions of features in the input and update features that do not overlap will be written to the output feature class. Computes a geometric union of the input features. All features and their attributes will be written to the output feature class. Overlay metrology is important for other reasons. Eventually, overlay data is combined with the critical dimension CD measurements on the device.

The numbers are crunched, resulting in a key figure that represents edge placement error EPE. EPE is the difference between the intended and the printed features of an IC layout. So, overlay metrology is critical, but it is becoming more challenging at each node. To put it in perspective, 2nm equates to ten atoms. In response, ASML and KLA-Tencor—the two main overlay metrology tool suppliers—are looking to solve the challenges, although they are taking slightly different approaches to the problem.

IBO uses built-in test patterns, which are located outside the chip for overlay measurements. For some layers, where you want to improve your total measurement uncertainty, then scatterometry-based solutions can be beneficial.

In fact, at advanced nodes, the industry is moving from IBO to scatterometry, at least for some of the more complex layers. IBO is still used for other layers. Scatterometry is sometimes referred to as diffraction-based overlay DBO. Used in the industry for years, DBO measures the changes in the intensity of light. Some engineers are comfortable with scatterometry.

Regardless, KLA-Tencor recently rolled out a new overlay metrology tool based on scatterometry. The system, dubbed the ATL, is a standalone product that features a tunable laser technology. Scatterometry enables precise on-product overlay measurements at high throughputs. However, the technology is more susceptible to process variations.

Instead, the measurements are taken on small objects called targets. Targets are pre-fabricated, diffraction-based structures. The target mimics the behavior of the device. To measure overlay, you create a film stack with gratings. A grating with a target is placed in the first layer. Then, another grating with a target is placed on top. The tool shines a light through the stack, resulting in a diffraction pattern. Source: KLA-Tencor. A mishap with the scanner and mask can cause overlay errors, but they are not the only culprits.

Films, processes and stress also contribute to errors. Errors can also crop up in the measurements themselves. At advanced nodes, though, it is becomes more challenging to detect misalignments and overlay errors. With that, it brings a lot of challenges with process integration schemes. Before, you used to see a lot of problems with lithography-related hotspots.

With the tunable laser, the metrology tool sweeps through the wafer at different wavelengths. It finds the area with the lowest inaccuracy. So when you have overlay, you can measure it accurately. Then, with the homing function, the tool looks for a region that represents the optimal point to measure, which saves time and money.

Figure 3: Schematic of automated process corrections update using KT Analyzer. This strategy is designed to improve the lithographic processes. As part of this multi-pronged strategy, ASML attempts to drive down the overlay accuracy on its scanner. The scanner itself incorporates several sensors, which collect data on and around the wafer. Then, the data is fed into the metrology tool. And finally, the data is crunched in a computational unit.

We call that computational overlay. You can predict the overlay rather than trying to measure it. Integrated metrology is one of two types of configurations in the arena. In integrated metrology, the metrology unit is incorporated into another piece of equipment.

As stated above, a standalone metrology system resides next to another system. With integrated metrology, the drawback is that it may slow down the scanner. Then, if an integrated metrology unit goes down, the data must be re-routed to a standalone system. On the other hand, integrated metrology saves floor space in the fab. That complexity has increased with the different mask levels and litho-etch-litho-etch scenarios.